Optimization of the BIOS
BIOS FEATURES SETUP
It is a question of the first one of the three most interesting paragraphs, although there are small the options of this one that we must be interested in facing the optimization:
External Cache: (in case of Pentium MMX treats 7 as a system with socket socket , for Pentium, K6, K6-2, K6-III, Cyrix MII or Winchip). (Enabled) should be activated, to allow our system to use the cache memory installed in our motherboard.
CPU Level 2 Cache: (for systems Pentium II/III, Celeron A, Athlon or Duron). It is the equivalent to the previous one, nevertheless the cache memory of the second level in these processors is in the mike, not in the badge; also (Enabled) should be activated.
CPU Level 1 Cache: the cache memory of the first level of the processor must always be activated (Enabled). If it deactivates it, it will see that his computer turns much leeentooo...
Memory parity/ECC Check: it activates the errors correction in the principal memory. If we activate this option and our memory supports ECC (frankly strange thing, except in quite expensive servants) it will diminish the yield but the reliability will increase. We recommend that to be deactivated (Disabled).
CPU Level 2 Cache ECC Checking: the same as earlier but for the level cache memory 2, the most logical thing in order to increase the yield is to deactivate (Disabled).
IDE HDD Block Mode: (Enabled) must be activated so that our hard disk supports the way of transference of blocks.
Video BIOS Shadow: we will copy part of the code of the BIOS of our graphic card in the RAM, accelerating the access to graphic functions, therefore we it must activate (Enabled).
CHIPSET FEATURES SETUP
The second important submenu, and perhaps the most influential. In this case we have enough interesting options that they affect to the yield:
System Memory Clock: typical option of basic badges with chipset Intel 815, that the speed of the memory allows to fit to 100 ó 133 MHz. The ideal thing will be the most rapid thing... that supports the memory, skylight.
DRAM Clock: an option similar to the previous, typical one of the badges with chipsets ROUTE. The speed of the memory allows to form to the same one that that of the bus ("Host Clock"; for example, 66 MHz in a Celeron) or to that of the bus more / less 33 MHz (the speed of the PCI).
SDRAM CAS-to-CAS Delay: the value must be a minimum (2 normally) to obtain the biggest services. A major value means, on the contrary, major stability.
SDRAM CAS latency: also it must be a minimum to obtain the biggest services. A higher value (3) increases the stability. It must be born in mind that although most of memoirs 2 support the value when they work to 100 MHz or less, working to 133 MHz only those of EXCEPTIONAL quality will support it.
Bank 0/1 (2/3, 4/5) DRAM timing: at least ns, more MHz, with what we will increase significantly the speed of transference of memory. In my case, with PC100, 60ns they are not giving me problems... but it is a question of trying.
SDRAM Leadoff Command: also it will have to have a minimal value to increase the yield.
SDRAM Precharge Control: if we activate it we can reduce the yield on having forced a continuous refreshment of the information in the memory, it is better it to deactivate (Disabled).
DRAM Read Pipeline: it will be better that we activate (Enabled) to increase the yield.
Cache Rd + CPU Wt Pipeline: also we will have to activate (Enabled) to accelerate the transference between the cache memory and the processor.
System BIOS Cacheable: we will have to activate (Enabled) to copy the code of the BIOS in the RAM and this way to gain access to him more quickly, on having been able to be located in the cache memory.
Video BIOS Cacheable: also we will activate (Enabled), in this case to copy the BIOS of our graphic card in the RAM, with what it can use the cache memory.
Video RAM Cacheable: some graphic devices allow the memory RAM of our graph to be able to use the cache memory for a more rapid access. If the graphic card supports it we it will have to activate (Enabled).
AGP Aperture Size: we will indicate the size of principal memory destined to the cards AGP. A major size implies a major information transit, and can saturate our memory. The most suitable thing is to prove diverse values, between 32MB and the memory of our system and to verify that one with which we obtain a major yield.
Spread Spectrum: it is an option that we will have to deactivate (Disabled).
CPU to PCI Write Buffer: we it will have to activate (Enabled). It will accelerate the communication of our processor with the BUS PCI.
PCI Dynamic Bursting: we it will have to activate (Enabled).
PCI Master's degree OWS Write: we it will have to activate (Enabled).
PCI Delay Transaction (or Delayed Transaction): the most logical thing would be to deactivate the delay (Disabled). But to fulfill the specifications PCI 2.1 (Enabled) will have to be activated.
PCI Master's degree Read Prefetch: we will have to activate this option (Enabled).
PCI #2 Acces PCI #1 Retry: we will have to activate (Enabled).
AGP Master's degree 1 WS Write/Read: both options will have to be activated to accelerate the behavior of the BUS AGP (Enabled).
Memory Hole at 15-16M: in normal conditions, we will always have to deactivate this option (Disabled).